1. Field of the Invention
The present invention relates to the field of semiconductor fabrication, and more particularly, to a method for forming a hard mask in semiconductor device fabrication and a method for fabricating a semiconductor device.
2. Description of the Related Art
With the development of integrated circuit techniques, the size of semiconductor devices is significantly reduced. In order to achieve smaller critical dimension (CD), requirement on lithographic resolution are continuously increased. However, due to limitations of lithography processes, it is difficult for patterns formed by direct lithography to meet the requirement for continuously decreased critical dimension. In order to address the limit of lithographic resolution, a double patterning technology (DPT) has been developed and utilized by designers, in which part of features of the desired pattern are transferred to a hard mask layer in each of two lithography steps, so as to obtain a hard mask pattern with a smaller linewidth. Etching is then carried out with the hard mask, allowing smaller critical dimensions to be achieved.
Generally, the double patterning technology may result in the linewidths on a single chip which are the same as the critical dimension. Some applications, however, require different linewidths on a single chip. For example, in NAND flash memory, peripheral and core portions of a single chip have different linewidths. A technique of achieving a hard mask with a smaller linewidth and thus doubling pattern density by doping sidewalls of a patterned silicon layer is disclosed in the U.S. patent publication No. 2011/0021010A1, filed on Jul. 27, 2009, entitled “METHOD FOR DOUBLE PATTERN DENSITY”. In this application, a method capable of achieving a hard mask pattern with different linewidths is proposed, which is schematically shown in FIG. 1. As shown in FIG. 1, a cap layer 122 is used as a mask to dope sidewalls of a silicon layer. As a result, doped portions 130 and 131 are obtained, which are then used as a hard mask to pattern the underlying material layer to be etched. In FIG. 1, the doped portions 131 in the right part of the silicon layer have a width of CDmin, which is a predetermined minimum linewidth. An undoped portion 132 is located between the two doped regions 131. On the other hand, the width W of the left part of the silicon layer is less than two times the CDmin (2*CDmin), so the doped side portions thereof adjoin each other to produce a single doped portion 130 having a width of W. Therefore, doped portions with different widths, such as portions 130 and 131 in FIG. 1, can be obtained by this method. After removing the cap layer 122 and the undoped portion 132, a hard mask pattern composed of doped portions can be obtained. However, such a method has some limitations; the maximum linewidth it can provide is only twice the minimum linewidth, namely, CDmin≦W≦2*CDmin.
Thus, the scheme shown in FIG. 1 can not provide more varied linewidths for chips having such a need. Therefore, it is desirable to provide a new technique to address the above problem.